The MIS (Metal Insulator Semiconductor) transistor is known as a semiconductor device from the past.
There are various fabrication methods of a gate insulator comprised in a MIS transistor, and one example is the technique of thermal oxidation, which is thermal oxidation treatment at approximately 800° C. or above using oxygen molecules and water molecules.
According to such a thermal oxidation technique, as a preprocess of the thermal oxidation process forming the gate insulator, processing to remove surface attached contaminants such as organic matter, metals and particles, followed by cleaning using diluted hydrofluoric acid and hydrogenated water, silicon dangling bonds on the surface of the silicon substrate (there are other semiconductor substrates such as germanium) on which the gate insulator is to be formed, are terminated by hydrogen, controlling formation of a native oxide film on the surface of the silicon substrate, and the silicon substrate with a clean surface is introduced to the following thermal oxidation process.
In this thermal oxidation process, heating of the silicon substrate is performed in an inert gas atmosphere such as argon (Ar). In this process of heating, surface-terminating hydrogen, which terminates the silicon dangling bonds on the surface of the silicon substrate, is removed with at a temperature of about 600° C. or higher, and oxidation of the surface of the silicon substrate is performed at a temperature of about 800° C. or higher in an atmosphere where oxygen molecules or water molecules are introduced.
When a silicon oxide film is formed on the surface of a silicon substrate using such a thermal oxidation technique, in the case of a silicon substrate with its surface being the crystal plane of the (100) plane orientation, oxide film/silicon interface characteristics, pressure-resistant characteristics of the oxide film, leakage current characteristics etc. are favorable. Other techniques alternative to the above thermal oxidation technique should yield the equivalent effect as well.
Then, in configuring an MIS transistor on a silicon substrate, a gate insulator is formed on the surface (the (100) plane) of a silicon substrate with the (100) plane being the principal plane, based on a technique such as the above thermal oxidation technique, and the insulator is comprised in a transistor (the p-channel MIS transistor and the n-channel MIS transistor) with a MIS configuration.
In addition, by forming an oxide film on a gate insulator using a technique such as the above thermal oxidation technique, a complementary MOS transistor (hereinafter referred to as a CMOS transistor) comprising a p-channel MOS (Metal Oxide Semiconductor) transistor and a n-channel MOS transistor can be integrated on the (100) plane of a silicon substrate.
On the other hand, semiconductor devices with a MOS transistor of distinctive gate configuration have appeared increasingly.
One example of those devices is a single conductivity type (the p-channel or the n-channel) MOS transistor configured by forming a gate insulator by applying the above thermal oxidation processing to one crystal plane (the (100) plane) of a projecting part formed on a semiconductor substrate and by forming channels on a sidewall plane of the projecting part of the semiconductor substrate (Japanese laid-open unexamined patent publication No. 2002-110963).
In general, when gate voltage is applied to an MIS transistor configured by forming the gate insulator on one crystal plane (the (100) plane), channels are formed in the silicon substrate. At that time, the channel width is provided by a length in a direction perpendicular to the direction of electron or hole movement along the channels formed along the one crystal plane.
In order to enhance the current driving capacity of the above MIS transistor, the electron transfer or hole transfer of the above channels are required to be enhanced, in order to realize the above, a design such that the above channel width should be lengthened, and such as to reduce waste of electrons and holes within the channel is required.
Patent Document 1: Japanese laid-open unexamined patent publication No. 2002-110963
However, in a general configuration of an MIS transistor, it is difficult to enhance the integrity of elements on a semiconductor because the element area of the MIS transistor increases as the channel width increases. In the case of adopting the technique disclosed in the Japanese laid-open unexamined patent publication No. 2002-110963, surplus electrons and holes are wasted depending on the plane orientation indicated by the semiconductor substrate projecting part on which channels are formed, and even if the energy amount, which is effective for driving a transistor, used for each unit length of the channel width is optimal in the (100) crystal plane, for example, it would be dramatically reduced in the other crystal planes.
When configuring a CMOS transistor, electron mobility has a value two or three times larger than hole mobility, and therefore, in order to match the current driving capacities to each other, the element area of a p-channel MOS transistor with small current driving capacity has to be made larger than that of an n-channel MOS transistor so that the channel width of the p-channel MOS transistor becomes large. Conversely, in the attempt to match the element areas, the channel widths become the same and thus the current driving capacities do not match.